HDL Works HDL Design Entry EASE v7.4.R1

Комплекс проектирования логических схем на языке VHDL и Verilog, содержащий в себе все самое необходимое.

EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language - VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project.

EASE Graphical Entry
EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in your preferred language - VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project.

Block Diagram Editor
The block diagram editor easily allows you to decompose your system into functional blocks. Automatic property propagation is featured to ensure consistency. Flexible and modular designs are developed through the use of generics and parameters. Automatic, incremental place and route of nets and buses is supported in addition to manual place and route of blocks to allow a fast, accurate and customized representation of your design.

Graphical Processes/Always Blocks
Facilitating an abstraction level between block diagrams and plain HDL code, EASE allows you to graphically represent VHDL processes or Verilog always statements. They can be placed as a block in a block diagram along with VHDL components or Verilog module instances, resulting in a much simpler design hierarchy. This approach yields a more compact HDL description and visualizes the data flow inside a single diagram.

State Diagram Editor
The state diagram editor supports Moore, Mealy and mixed state machines. Any valid VHDL expression or Verilog statement can be used to define actions and transition conditions. Transitions can be synchronous or asynchronous; outputs can be clocked or combinatorial. The state diagram editor supports a variety of state assignment methods, including binary, gray, one-hot and two-hot. User defined assignment is also supported. The generated HDL is optimized for time and area to achieve the best possible synthesized design from leading synthesis tools.

ОС: WinAll
Язык: английский
Лекарство: crack BEAN
Размер: 36.66 Mb

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